The term "circuit simulator" is used in this document to mean any of the family of design tools used to simulate the operation of electronic circuits, including analog circuit simulators, logic simulators, and HDL simulators.
The term "waveform" is used in this document to mean a sequence of values associated with a signal over a period of time, or equivalently, a sequence of one or more changes in the value of a signal over a period of time.
The detailed circuit specification used by circuit simulators and other circuit design tools is often called a netlist, and comprises a list of circuit components and the interconnections between those components. Circuit components are also known as "cells" where each cell in a specific circuit library has both a logical representation, as well as a circuit layout representation.
The netlist defines all of the interconnections between the components of the circuit. Each "signal" which interconnects two or more cells, or which represents an input or output for the entire circuit, is actually a node in the circuit which has been assigned a name. The terms "net," "signal" and "node" are often used interchangeably.
In addition, the netlist specifies the nature of its components by specifying a cell name for each component. The cell name, in turn, specifies or points to a particular circuit in a predefined library of cells.
Circuits can also be represented by a list of statements in a Hardware Description Language (HDL), such as Verilog or VHDL. The HDL circuit description is then converted into a specific circuit netlist either by an engineer or by an HDL circuit synthesizer using a specified set of library cells. Complex custom integrated circuits (ICs) are often designed by engineers at the "HDL level" and are specified by those engineers for simulation and verification purposes using an HDL circuit description such as a Verilog language circuit description.
Verifying the correctness of complex custom integrated circuits (ICs) and application specific integrated circuits (ASICs) or complete systems is a difficult and complicated task. In order to create the necessary conditions to detect defects in a circuit design, highly parallel but well-controlled verification programs must be written. In such programs, test patterns must be applied to the circuit's input ports and signals at the output ports must be observed over time to determine whether the inputs were transformed into the expected outputs. A computer based model of the circuit design that is being tested is generally referred to as the device under test (DUT). The testing verifies functional correctness, not manufacturing faults.
In the prior art, the most common method used to accomplish this task is to "surround" the DUT with a layer of code that performs the stimulus generation and output comparisons. This layer of code, often referred to as a test bench, can be very simple or as complex as necessary for the application at hand.
In the prior art, one difficulty in creating complex test benches arises when there are many types of events that are not expected to happen at specific times, but rather "some time" within a certain relationship to other events. For example, in a bus transaction, a designer might send a request and want to have it acknowledged within a certain window of time. However, whether the reply comes within 2 or 20 cycles might be irrelevant. Similarly, an arbiter may assign a given resource in ways that are difficult to predict and may not matter. What will actually matter is that in the end all the requests presented to the arbiter for servicing are satisfied by the arbiter and that the ordering satisfies a specified general policy.
These two examples reflect a common problem in the verification of complex circuits, namely that the inherently parallel nature of complex electronic circuits results in time and ordering ambiguities or uncertainties. A circuit designer seeking to verify such a complex circuits needs to be able to describe what is the expected behavior, without over-specifying exactly what should happen when.
Accordingly, it is the object of the present invention to provide a circuit verification system that is capable of verifying the operational correctness and performance characteristics of complex circuits, while enabling such criteria to be defined without having to precisely define exactly when associated signal combinations must occur. It is also an object of the present invention to provide a circuit verification system that can specify circuit correctness and performance criteria while accommodating signal ordering ambiguities.